PHP50N03LT Datasheet, PDF (4/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
Drain Current, ID (A)
50
VGS = 10 V 5 V
45
4.5 V
Tj = 25 C
40
35
3.2 V
30
3V
25
20
2.8 V
15
2.6 V
10
2.4 V
5
2.2 V
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Drain-Source Voltage, VDS (V)
Fig.5. Typical output characteristics
I_D = f(V_DS); parameter V_GS
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.2 V
2.6 V
0.09
2.4 V
2.8V
0.08
3V
Tj = 25 C
0.07
3.2 V
0.06
0.05
0.04
0.03
5V
VGS =4.5 V
0.02
0.01
0
0
10V
5 10 15 20 25 30 35 40 45 50
Drain Current, ID (A)
Fig.6. Typical on-state resistance
R_DS(ON) = f(I_D); parameter V_GS
Drain current, ID (A)
40
VDS > ID X RDS(ON)
35
30
25
20
15
10
175 C
5
Tj = 25 C
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
I_D = f(V_GS)
Transconductance, gfs (S)
30
VDS > ID X RDS(ON)
25
Tj = 25 C
175 C
20
15
10
5
0
0
5
10
15
20
25
30
35
40
Drain current, ID (A)
Fig.8. Typical transconductance
g_fs = f(I_D)
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j)
Threshold Voltage, VGS(TO) (V)
2.25
2
maximum
1.75
1.5
typical
1.25
1
minimum
0.75
0.5
0.25
0
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
October 1999
4
Rev 1.800