PHP50N03LT Datasheet, PDF (1/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
FEATURES
SYMBOL
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
• Logic level compatible
d
g
s
QUICK REFERENCE DATA
V_DSS = 25 V
I_D = 48 A
R_DS(ON) ≤ 16 mΩ (V_GS = 10 V)
R_DS(ON) ≤ 21 mΩ (V_GS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D²PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D²PAK)
PIN DESCRIPTION
tab
tab
1 gate
SOT428 (DPAK)
tab
2 drain ¹
3 source
tab drain
1 23
2
13
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
V_GSM
I_D
I_DM
P_tot
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_j ≤ 150˚C
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
48
34
180
86
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800