BUJ105A Datasheet, PDF (4/7 Pages) NXP Semiconductors – Silicon Diffused Power Transistor

Philips Semiconductors
Silicon Diffused Power Transistor
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0
20 40 60 80 100 120 140
Tmb / C
Fig.7. Normalised power dissipation.
PD% = 100⋅PD/PD _25˚C = f (T_mb)
HFE
50
30
20
15
10
5
Tj=100C
-40C
25C
2
VCE=1V
0.01
Fig.8.
0.05 0.1
0.3
IC/A
1
23
5
10
Typical DC current gain. h_FE = f(I_C)
parameter V_CE
HFE
50
30
20
15
10
Tj=100C
25C
-40C
5
VCE=5V
2
0.01
Fig.9.
0.05 0.1
0.3
IC/A
1
23
5
10
Typical DC current gain. h_FE = f(I_C)
parameter V_CE
Product specification
BUJ105A
VCEsat/V
2.0
1.6
IC=1A 2A 3A 4A
1.2
0.8
0.4
0.0
0.01
0.10
1.00
IB/A
10.00
Fig.10. Collector-Emitter saturation voltage.
Solid lines = typ values, V_CEsat = f(IB); T_j=25˚C.
VBESAT/V
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-40C
25C
Tj=100C
0.6
0.5
0.1
0.5
1
2
IC/A
5
10
Fig.11. Base-Emitter saturation voltage.
Solid lines = typ values, V_BEsat = f(IC); at IC/IB =4.
VCESAT/V
0.6
0.5
0.4
Tj=100C
0.3
0.2
0.1
25C
-40C
0
0.2
0.4
0.6
1
2
IC/A
56
Fig.12. Collector-Emitter saturation voltage.
Solid lines = typ values, V_CEsat = f(IC); at IC/IB =4.
February 1999
4
Rev 1.000