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74HC109 Datasheet, PDF (4/9 Pages) NXP Semiconductors – Dual JK flip-flop with set and reset; positive-edge trigger | |||
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Philips Semiconductors
Dual JK ï¬ip-ï¬op with set and reset;
positive-edge trigger
Product speciï¬cation
74HC/HCT109
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING
INPUTS
MODE
SD
RD
CP
J
K
asynchronous set
L
H
X
X
X
asynchronous reset H
L
X
X
X
undetermined
L
L
X
X
X
toggle
H
H
â
h
l
load â0â (reset)
H
H
â
l
l
load â1â (set)
H
H
â
h
h
hold âno changeâ
H
H
â
l
h
OUTPUTS
Q
Q
H
L
L
H
H
H
q
q
L
H
H
L
q
q
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = donât care
â = LOW-to-HIGH CP transition
handbook, full pagewidth
K
J
S
R
CP
C
C
C
C
C
C
Q
C
C
Q
C
C
MBK217
Fig.5 Logic diagram (one flip-flop).
PACKAGE OUTLINES
See â74HC/HCT/HCU/HCMOS Logic Package Outlinesâ.
1997 Nov 25
4
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