P89LPC924_925 Datasheet, PDF(30/49 Page) NXP Semiconductors – 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter

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P89LPC924_925 Datasheet, PDF (30/49 Pages) NXP Semiconductors – 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter

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Philips Semiconductors

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

8.19.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is â1â, framing errors can be made available in SCON.7 respectively. If

SMOD0 is â0â, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)

are set up when SMOD0 is â0â.

8.19.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device and force the device into ISP mode.

8.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ï¬rst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = â0â), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = â0â).

8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

9397 750 14471

Product data

Rev. 03 â 15 December 2004

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