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PZ3064 Datasheet, PDF (3/20 Pages) NXP Semiconductors – 64 macrocell CPLD
Philips Semiconductors
64 macrocell CPLD
Product specification
PZ3064
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
PZ3064-10A44
PZ3064-12A44
PZ3064I12A44
PZ3064I15A44
PZ3064-10BC
PZ3064-12BC
PZ3064I12BC
PZ3064I15BC
PZ3064-10A68
PZ3064-12A68
PZ3064I12A68
PZ3064I15A68
PZ3064-10A84
PZ3064-12A84
PZ3064I12A84
PZ3064I15A84
PZ3064-10BB1
PZ3064-12BB1
PZ3064I12BB1
PZ3064I15BB1
44-pin PLCC, 10ns tPD
44-pin PLCC, 12ns tPD
44-pin PLCC, 12ns tPD
44-pin PLCC, 15ns tPD
44-pin TQFP, 10ns tPD
44-pin TQFP, 12ns tPD
44-pin TQFP, 12ns tPD
44-pin TQFP, 15ns tPD
68-pin PLCC, 10ns tPD
68-pin PLCC, 12ns tPD
68-pin PLCC, 12ns tPD
68-pin PLCC, 15ns tPD
84-pin PLCC, 10ns tPD
84-pin PLCC, 12ns tPD
84-pin PLCC, 12ns tPD
84-pin PLCC, 15ns tPD
100-pin PQFP, 10ns tPD
100-pin PQFP, 12ns tPD
100-pin PQFP, 12ns tPD
100-pin PQFP, 15ns tPD
DESCRIPTION
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
DRAWING NUMBER
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT376-1
SOT376-1
SOT376-1
SOT376-1
SOT188-3
SOT188-3
SOT188-3
SOT188-3
SOT189-3
SOT189-3
SOT189-3
SOT189-3
SOT382-1
SOT382-1
SOT382-1
SOT382-1
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin tPD of the PZ3064 device through the PAL array is
10ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin tPD for the PZ3064 using 6 to 37 product terms is
12.5ns (10ns for the PAL + 2.5ns for the PLA).
1997 Mar 05
83