PUSB3F96_15 Datasheet, PDF (3/15 Pages) NXP Semiconductors – ESD protection for ultra high-speed interfaces

NXP Semiconductors
PUSB3F96
ESD protection for ultra high-speed interfaces
6. Characteristics
Table 5. Characteristics
T_amb = 25 C unless otherwise specified.
Symbol Parameter
Conditions
V_BR
I_LR
V_F
C_line
C_line
breakdown voltage
reverse leakage current
forward voltage
line capacitance
line capacitance
difference
I_I = 1 mA
per channel; V_I = 3 V
I_I = 1 mA
f = 1 MHz; V_I = 3.3 V
f = 1 MHz; V_I = 3.3 V
r_dyn
dynamic resistance
surge
positive transient
negative transient
TLP
positive transient
negative transient
V_CL
clamping voltage
I_PP = 5.2 A
positive transient
I_PP = 4.4 A
negative transient
[1] This parameter is guaranteed by design.
[2] According to IEC 61000-4-5 (8/20 s current waveform).
[3] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns.
Min
6
-
-
[1] _-
[1] _-
Typ
-
-
0.7
0.5
0.05
Max Unit
-
V
1
A
-
V
0.6 pF
-
pF
[2]
-
0.41 -

-
0.26 -

[3]
-
0.43 -

-
0.28 -

[2]
-
4.6 -
V
[2]
-
2.2 -
V
PUSB3F96
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 29 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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