PUSB3F96_15 Datasheet, PDF (11/15 Pages) NXP Semiconductors – ESD protection for ultra high-speed interfaces

NXP Semiconductors
9. Soldering
PUSB3F96
ESD protection for ultra high-speed interfaces
Footprint information for reflow soldering of DFN2510A-10 package
SOT1176-1
Hx
C
Hy Ay By
0.05
D
P
0.05
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
P
Ay
By
C
D
Hx
Hy
0.5 1.25 0.3 0.475 0.2 2.45 1.5
Remark:
Stencil of 75 μm is recommended.
A stencil of 75 μm gives an aspect ratio of 0.77
With a stencil of 100 μm one will obtain an aspect ratio of 0.58
Fig 17. Reflow soldering footprint DFN2510A-10 (SOT1176-1)
sot1176-1_fr
PUSB3F96
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 29 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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