PHX3055L Datasheet, PDF (3/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Preliminary specification
PHX3055L
120 ^PD%
110
Normalised Power Derating
with heatsink compound
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ths / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_hs)
ID%
120
110
Normalised Current Derating
with heatsink compound
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ths / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_hs); conditions: V_GS ≥ 10 V
ID, Drain current (Amps)
100
10
RDS(ON) ^{= VDS/ID}
DC
1
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.1
1
10
100
VDS, Drain-source voltage (Volts)
1000
Fig.3. Safe operating area. T_hs = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth(j-hs)
10
Transient Thermal Impedance (K/W) PHX3055E
0.5
1 _0.2
0.1
0.05
0.1 0.02
0.01
0
P_D
tp
D
=
tp
T
T
t
0.001
1us 10us 100us 1ms 10ms 0.1s 1s 10s
tp, pulse width (s)
Fig.4. Transient thermal impedance.
Z_{th j-hs} = f(t); parameter D = t_p/T
ID, Drain current (Amps)
15
10 V
10
5
Tj = 25 C
PHP3055E
7V
6.5 V
6V
5.5 V
5V
VGS = 4.5 V
0
0
5
10
15
20
25
30
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics.
I_D = f(V_DS); parameter V_GS
RDS(on), Drain-Source on resistance (Ohms) PHP3055E
0.4
5.5 V 6 V 6.5 V 7 V
0.3
0.2
10 V
0.1
VGS = 15 V
Tj = 25 C
0
0
5
10
15
20
ID, Drain current (Amps)
Fig.6. Typical on-state resistance.
R_DS(ON) = f(I_D); parameter V_GS
October 1997
3
Rev 1.000