PHX3055L Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Preliminary specification
PHX3055L
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope. The
device features high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
60
9.4
28
0.18
UNIT
V
A
W
Ω
PINNING - SOT186A
PIN
DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
I_D
Continuous drain current
I_DM
P_D
∆P_D/∆T_hs
V_GS
V_GSM
E_AS
I_AS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Non-repetitive gate source
voltage
Single pulse avalanche
energy
Peak avalanche current
T_j, T_stg
Operating junction and
storage temperature range
T_hs = 25 ˚C; V_GS = 10 V
T_hs = 100 ˚C; V_GS = 10 V
T_hs = 25 ˚C
T_hs = 25 ˚C
T_hs > 25 ˚C
t_p≤50µs
V_DD ≤ 50 V; starting T_j = 25˚C; R_GS = 50 Ω;
V_GS = 10 V
V_DD ≤ 50 V; starting T_j = 25˚C; R_GS = 50 Ω;
V_GS = 10 V
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
9.4
5.9
26
28
0.22
± 15
± 20
25
6
150
UNIT
A
A
A
W
W/K
V
V
mJ
A
˚C
ISOLATION LIMITING VALUE & CHARACTERISTIC
T_hs = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V_isol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
three terminals to external
waveform;
heatsink
R.H. ≤ 65% ; clean and dustfree
C_isol
Capacitance from T2 to external f = 1 MHz
heatsink
MIN. TYP. MAX. UNIT
-
2500 V
-
10
-
pF
October 1997
1
Rev 1.000