PDI1394P22 Datasheet, PDF (3/30 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
4.0 PIN CONFIGURATION
Objective specification
PDI1394P22
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LREQ 1
DGND 2
CTL0 3
CTL1 4
D0 5
D1 6
DVDD 7
D2 8
D3 9
PDI1394P22
D4 10
D5 11
D6 12
D7 13
DGND 14
CNA 15
LPS 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 TPBIAS2
47 TPA2+
46 TPA2–
45 TPB2+
44 TPB2–
43 AVDD
42 TPBIAS1
41 TPA1+
40 TPA1–
39 TPB1+
38 TPB1–
37 TPBIAS0
36 TPA0+
35 TPA0–
34 TPB0+
33 TPB0–
SV001782
5.0 PIN DESCRIPTION
Name
Pin Type
Pin Numbers
AGND
Supply
32, 49, 52, 53
AVDD
Supply
30, 31, 43, 50, 51
CNA
CPS
CTL0,
CTL1
CMOS
15
CMOS
24
CMOS 5V tol 3, 4
I/O
Description
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
I
Cable Power Status input. This terminal is normally connected to cable
power through a 370–410 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P22 and the LLC. Bus holders are built into
these terminals.
1999 Jul 09
3