PDI1394P22 Datasheet, PDF (17/30 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P22
17.1 External Component Connections
V_DD
12 pF
12 pF
24.576 MHz
0.1 µF
6.34 kΩ
±1%
0.1 µF
0.001 µF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
0.3–1.0 µF
1 LREQ
TPBIAS2 48
2 DGND
TPA2+ 47
3 CTL0
TPA2– 46
4 CTL1
TPB2+ 45
5 D0
TPB2– 44
6 D1
AVDD 43
7 DVDD
TPBIAS1 42
8 D2
9 D3
PDI1394P22
TPA1+ 41
TPA1– 40
10 D4
TPB1+ 39
11 D5
TPB1– 38
12 D6
TPBIAS0 37
13 D7
TPA0+ 36
14 DGND
TPA0– 35
CNA OUT 15 CNA
LINK PULSE 16 LPS
OR V_DD
TPB0+ 34
TPB0– 33
REFER TO
FIGURE 7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TPBIAS
TP CABLES
INTERFACE
CONNECTION
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE
CONNECTION
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE
CONNECTION
10 kΩ
370–
410 kΩ
See Figure 6 for recommended power and ground connections.
Figure 8. External Component Connections
1999 Jul 09
17
SV001783