BUK104-50L Datasheet, PDF (3/14 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK104-50L/S
BUK104-50LP/SP
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN. MAX. UNIT
I_DRRM
E_DSM
E_DRM
Repetitive peak clamping drain current R_IS ≥ 100 Ω¹
Non-repetitive inductive turn-off
energy²
I_DM = 15 A; R_IS ≥ 100 Ω
Repetitive inductive turn-off energy
R_IS ≥ 100 Ω; T_mb ≤ 95 ˚C;
I_DM = 4 A; V_DD ≤ 20 V;
f = 250 Hz
-
15
A
-
200
mJ
-
20
mJ
I_DIRM
Repetitive peak drain to input current³ R_IS = 0 Ω; t_p ≤ 1 ms
-
50
mA
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
I_S
Continuous forward current
CONDITIONS
T_mb = 25 ˚C;
V_IS = V_PS = V_FS = 0 V
MIN.
-
MAX.
15
UNIT
A
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
Thermal resistance
R_{th j-mb}
R_{th j-a}
Junction to mounting base
Junction to ambient
CONDITIONS
-
in free air
MIN. TYP. MAX. UNIT
-
2.5 3.1 K/W
-
60
- K/W
STATIC CHARACTERISTICS
T_mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V_(CL)DSR
V_(CL)DSR
I_DSS
I_DSR
I_DSR
Drain-source clamping voltage
Drain-source clamping voltage
Zero input voltage drain current
Drain source leakage current
Drain source leakage current
R_IS = 100 Ω; I_D = 10 mA
R_IS = 100 Ω; I_DM = 1 A; t_p ≤ 300 µs;
δ ≤ 0.01
V_DS = 12 V; V_IS = 0 V
V_DS = 50 V; R_IS = 100 Ω;
V_DS = 40 V; R_IS = 100 Ω;
T_j = 125 ˚C
R_DS(ON)
Drain-source on-state
resistance
I_DM = 7.5 A;
t_p ≤ 300 µs; δ ≤ 0.01
V_IS = 7 V
V_IS = 5 V
MIN.
50
50
TYP.
-
-
MAX.
65
70
UNIT
V
V
-
0.5 10 µA
-
1
20 µA
-
10 100 µA
-
75 100 mΩ
-
95 125 mΩ
1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to
become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS.
2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at
energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source
voltage becoming positive.
January 1993
3
Rev 1.200