74F552 Datasheet, PDF (3/14 Pages) NXP Semiconductors – Octal registered transceiver with parity and flags 3-State

Philips Semiconductors
Octal registered transceiver with parity and flags (3-State)
Product specification
74F552
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
A0–A7
A Data inputs
3.5/1.0
B0–B7
B Data inputs
3.5/1.0
CPR
R registers clock input (active rising edge)
1.0/1.0
CPS
S registers clock input (active rising edge)
1.0/1.0
CER
R registers clock Enable input (active Low)
1.0/1.0
CES
S registers clock Enable input (active Low)
1.0/1.0
OEBR
A-to-B Output Enable input (active Low)
and clear FS output (active Low)
1.0/2.0
OEAS
B-to-A Output Enable input (active Low)
and clear FR output (active Low)
1.0/2.0
PARITY
Parity bit transceiver input
Parity bit transceiver output
3.5/1.0
750/106.7
ERROR
Parity check output (active Low)
50/33.3
A0–A7
A Data outputs
150/40
B0–B7
B Data outputs
750/106.7
FR
A-to-B Status Flag output (active High)
50/33.3
FS
B-to-A Status Flag output (active High)
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
50/33.3
LOAD VALUE
HIGH/LOW
70µA/0.6mA
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
70µA/0.6mA
15mA/64mA
1.0mA/20mA
3.0mA/24mA
15mA/64mA
1.0mA/20mA
1.0mA/20mA
FUNCTIONAL DESCRIPTION
Data applied to the A inputs are entered and stored on the rising
edge of the CPR clock pulse, provided that the CER is Low;
simultaneously, the status flip-flop is set and the A-to-B flag (FR)
output goes High. As the CER returns to High, the data will be held
in R register. This data entered from the A inputs will appear at the B
port I/O pins after the OEBR has gone Low. When OEBR is Low, a
parity bit appears at the PARITY pin, which will be set High when
there is an even number of 1s or all 0s at the Q outputs of the R
register. After the data is assimilated, the receiving system clears
the flag FR, by changing the signal at the OEBR pin from Low to
High. Data flow from B-to-A proceeds in the same manner described
for A-to-B flow. A Low at the CES pin and a Low-to-High transition at
the CPS pin enters the B input data and the parity input data into the
S register and the parity register respectively and set the flag output
FS to High. A Low signal at the OEAS pin enables the A port I/O
pins and a Low-to-High transition of the OEAS signal clears the FS
flag. When OEAS is Low, the parity check output ERROR will be
High if there is an odd number of 1s at the Q outputs of the S
register and the parity register.
R or S REGISTER FUNCTION TABLE
INPUTS
OUTPUTS
An or Bn CPX CEX INTERNAL Q
X
X
H
NC
L
↑
L
L
H
↑
L
H
X
↑
L
NC
H = High voltage level
L = Low voltage level
NC= No change
X = Don’t care
X = R or S for CPX and CEX
↑ = Low-to-High transition
↑ _{= Not Low-to-High transition}
OPERATING
MODE
Hold data
Load data
Keep old data
OUTPUT CONTROL TABLE
INPUT
OEXX
OUTPUTS
INTERNAL Q
An or Bn
H
X
Z
L
L
L
L
H
H
H = High voltage level
L = Low voltage level
X = Don’t care
XX= AS or BR
Z = High impedance “off” state
OPERATING
MODE
Disable outputs
Enable outpus
1991 Jan 02
3