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PCF50732 Datasheet, PDF (26/64 Pages) NXP Semiconductors – Baseband and audio interface for GSM
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Philips Semiconductors
Baseband and audio interface for GSM
Objective specification
PCF50732
12.3.2 AUXDAC1 (AGC) VALUE AND AUXDAC2 (AFC) VALUE REGISTERS
Table 14 Registers overview
X = don’t care during a read/or write access.
ADDR.
REGISTER NAME
0001 AUXDAC1 (AGC) value register
0010 AUXDAC2 (AFC) value register
VALUE
11 10 9 8 7 6 5 4 3 2 1 0
X X X X b7 b6 b5 b4 b3 b2 b1 b0
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Table 15 AUXDAC1 (AGC) value and AUXDAC2 (AFC) value registers value description
VALUE OF
SYMBOL
DESCRIPTION
AUXDAC1 (AGC) value register b7 to b0 input value to the 8-bit AUXDAC1 (fed directly into the DAC); the default
value is 85H
AUXDAC2 (AFC) value register b11 to b0 input value to the 8-bit AUXDAC2 (fed directly into the DAC); the default
value is 800H
12.3.3 BURST CONTROL REGISTER
The Burst control register controls the timing of the transmit burst (TX-burst). The ‘lo’-registers contain the lower 8 bits,
the ‘hi’-registers the upper 4 bits of a 12-bit delay value. Therefore, each register has a programmable range
from 0 to 4095. Not all combinations of values might make sense e.g. ramp-down before ramp-up.
Table 16 Burst control register (address 001 and subaddresses)
X = don’t care during a read/or write access.
FUNCTION
RU-lo
RU-hi
RM-lo
RM-hi
RD-lo
RD-hi
BIEN0-lo
BIEN0-hi
BIEN1-lo
BIEN1-hi
Single/double burst mode(1)
DAC3 burst RAM address(1)
DAC3 burst RAM data(1)
SUBADDRESS
VALUE
11 10 9
8
(s3) (s2) (s1) (s0)
7
6
5
4
3
2
1
0
0
0
0
0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
1
X X X X b11 b10 b9 b8
0
0
1
0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
1
1
X X X X b11 b10 b9 b8
0
1
0
0 b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
1
X X X X b11 b10 b9 b8
0
1
1
0 b7 b6 b5 b4 b3 b2 b1 b0
0
1
1
1
X X X X b11 b10 b9 b8
1
0
0
0 b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
1
X X X X b11 b10 b9 b8
1
0
1
0
X X X X X X X b0
1
0
1
1
X X a5 a4 a3 a2 a1 a0
1
1 d9(2) d8(2) d7 d6 d5 d4 d3 d2 d1 d0
Notes
1. The programming is described in Section 9.3.2.2.
2. The subaddress positions bit 9 (s1) and bit 8 (s0) do not apply to the DAC3 burst RAM data register.
1999 May 03
26
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