PCA21125 Datasheet, PDF (26/42 Pages) NXP Semiconductors – SPI-bus Real-Time Clock and calendar

NXP Semiconductors
PCA21125
SPI-bus Real-Time Clock and calendar
The setting of this mode requires that bit POR_OVRD (register Control_1, see Table 5) be
set logic 1 and that the signals at the SPI-bus pins SDI and CE are toggled as illustrated in
Figure 17. All timings are required minimums.
Once the override mode has been entered, the device immediately stops being reset and
set-up operation can commence, i.e., entry into the external clock test mode via the
SPI-bus access. The override mode can be cleared by writing logic 0 to bit POR_OVRD.
Bit POR_OVRD must be set logic 1 before a re-entry into the override mode is possible.
Setting bit POR_OVRD logic 0 during normal operation has no effect except to prevent
accidental entry into the POR override mode. This is the recommended setting.
8.11 3-line SPI-bus
Data transfer to and from the device is made via a 3-line SPI-bus; see Table 38.
Table 38. Serial interface
Pin Function
Description
CE chip enable input when HIGH, data transfer is active
when LOW, data transfer is inactive; the interface is reset; pull-down
resistor included; active input can be higher than V_DD, but must not
be wired HIGH permanently
SCL
SDI
SDO
serial clock input
serial data input
serial data output
when pin CE = LOW, this input might float; input can be higher than
V_DD
when pin CE = LOW, this input might float; input can be higher than
V_DD; input data is sampled on the rising edge of SCL
push-pull output; drives from V_SS to V_DD; output data is changed on
the falling edge of SCL
The data lines for input and output are split. The data input and output lines can be
connected together to facilitate a bidirectional data bus (see Figure 18).
SDI
SDO
SDI
SDO
two wire mode
Fig 18. SDI, SDO configurations
single wire mode
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The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte, with the Most Significant Bit (MSB) sent first; see Figure 19.
data bus
chip enable
COMMAND
DATA
Fig 19. Data transfer overview
DATA
DATA
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PCA21125_1
Product data sheet
Rev. 01 — 16 November 2009
© NXP B.V. 2009. All rights reserved.
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