TDA1315H Datasheet, PDF (25/36 Pages) NXP Semiconductors – Digital audio input/output circuit DAIO

Philips Semiconductors
Digital audio input/output circuit (DAIO)
Product specification
TDA1315H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
IECIN1 (PIN 5)
V_i(p-p)
AC input voltage
0.2
(peak-to-peak value)
I_i
V_bias
input current
DC bias voltage
V_I = 0 or 5 V; V_DD = 5 V
−
−
I²S-bus interface; (for timing see Chapter “References”, item 3)
−
±550
0.5V_DD
SD INPUT/OUTPUT (PIN 35)
t_dSDAUX
output delay with
respect to SDAUX
−
−
Microcontroller interface (see Figs 6 and 7)
T
t_HC
t_LC
t_SU;AD
t_HD;AD
t_SU;MA
t_HD;MA
t_SU;MT
t_HD;MT
t_SU;DA
t_HD;DA
t_EN;DT
t_HD;DT
t_3DT
t_halt
LCLK period
LCLK HIGH period
LCLK LOW period
LADDR set-up time
LADDR hold time
LMODE set-up time
LMODE hold time
LMODE set-up time
LMODE hold time
LDATA set-up time
LDATA hold time
LDATA enable time
LDATA hold time
LDATA disable time
LMODE halt time
T_c + 50
−
25
−
25
−
25
−
25
−
addressing mode
addressing mode
1_{⁄2(Tc + 50) −}
1_{⁄2(Tc + 50) −}
halt mode
25
−
halt mode
25
−
write and addressing mode 25
−
write and addressing mode 25
−
data read mode
−
−
data read mode; note 3
1_⁄2Tc
−
data read mode
−
−
0
−
Mode switching and STROBE (see Fig.10)
t_H;SB
t_L;SB
t_SU;SB
STROBE HIGH time
STROBE LOW time
set-up time before
STROBE
for pins or bits
3T_c + 50 −
3T_c + 50 −
−T_c + 50 −
t_HD;SB
t_DBIT
hold time after STROBE for pins or bits
delay LCLK to internal control register
bit
2T_c + 50 −
2T_c
−
t_EN;SD
t_3SD
SD enable time
SD and INVALID disable
time
T_c
−
−
−
t_EN;WS
WS, SCK and INVALID
enable time
T_c
−
t_3WS
WS and SCK disable
time
T_c
−
t_EN;CO
SYSCLKO enable time
T_c
−
1995 Jul 17
25
MAX.
UNIT
V_DD
V
−
µA
−
V
50
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
50
ns
T_c + 50 ns
50
ns
−
ns
−
ns
−
ns
−
ns
−
ns
3T_c + 50 ns
2T_c + 50 ns
T_c + 50 ns
2T_c + 50 ns
2T_c + 50 ns
2T_c + 50 ns