XA-G37 Datasheet, PDF (24/37 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K OTP, 512 B RAM, watchdog, 2 UARTs

Philips Semiconductors
XA 16-bit microcontroller family
32K OTP, 512 B RAM, watchdog, 2 UARTs
Product data
XA-G37
AC ELECTRICAL CHARACTERISTICS
V_DD = 2.7 V to 5.5 V; T_amb = 0 to +70 °C for commercial, –40 °C to +85 °C for industrial.
SYMBOL FIGURE
PARAMETER
External Clock
f_C
t_C
22
t_CHCX
22
t_CLCX
22
t_CLCH
22
t_CHCL
22
Oscillator frequency
All devices except PXAG37KFx
PXAG37KFx
V_DD = 2.85 V to 5.5 V
T_amb = –40 °C to +85 °C
V_DD = 2.7 V to 2.85 V
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
AC ELECTRICAL CHARACTERISTICS (V_DD = 4.5 V TO 5.5 V)
T_amb = 0 to +70 °C for commercial, –40 °C to +85 °C for industrial.
SYMBOL FIGURE
PARAMETER
Address Cycle
t_CRAR
21
t_LHLL
16
t_AVLL
16
t_LLAX
16
Code Read Cycle
t_PLPH
16
t_LLPL
16
t_AVIVA
16
t_AVIVB
17
t_PLIV
16
t_PXIX
16
t_PXIZ
16
t_IXUA
16
Data Read Cycle
t_RLRH
18
t_LLRL
18
t_AVDVA
18
t_AVDVB
19
t_RLDV
18
t_RHDX
18
t_RHDZ
18
t_DXUA
18
Data Write Cycle
t_WLWH
20
t_LLWL
20
t_QVWX
20
t_WHQX
20
t_AVWL
20
t_UAWH
20
Wait Input
t_WTH
21
t_WTL
21
NOTES ON PAGE 23.
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non-ALE cycle (access time)
PSEN asserted to instruction valid (enable time)
Instruction hold after PSEN de-asserted
Bus 3-State after PSEN de-asserted (disable time)
Hold time of unlatched part of address after instruction latched
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non-ALE cycle (access time)
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after data latched
WR pulse width
ALE falling edge to WR asserted
Data valid before WR asserted (data setup time)
Data hold time after WR de-asserted (Note 6)
Address valid to WR asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR is de-asserted
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
2002 Mar 25
22
VARIABLE CLOCK
MIN
MAX
UNIT
0
0
0
1/f_C
t_C * 0.5
t_C * 0.4
30
MHz
30
MHz
25
MHz
ns
ns
ns
5
ns
5
ns
VARIABLE CLOCK
MIN
MAX
UNIT
10
46
ns
(V1 * t_C) – 6
ns
(V1 * t_C) – 12
ns
(t_C/2) – 10
ns
(V2 * t_C) – 10
ns
(t_C/2) – 7
ns
(V3 * t_C) – 36
ns
(V4 * t_C) – 29
ns
(V2 * t_C) – 29
ns
0
ns
t_C – 8
ns
0
ns
(V7 * t_C) – 10
ns
(t_C/2) – 7
ns
(V6 * t_C) – 36
ns
(V5 * t_C) – 29
ns
(V7 * t_C) – 29
ns
0
ns
t_C – 8
ns
0
ns
(V8 * t_C) – 10
ns
(V12 * t_C) – 10
ns
(V13 * t_C) – 22
ns
(V11 * t_C) – 5
ns
(V9 * t_C) – 22
ns
(V11 * t_C) – 7
ns
(V10 * t_C) – 30 ns
(V10 * t_C) – 5
ns