SC16C654B Datasheet, PDF (24/58 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder

Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7. Register descriptions
Table 8 details the assigned bit functions for the SC16C654B/654DB internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 8: SC16C654B/654DB internal registers
A2 A1 A0 Register Default ^[1] Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
General Register Set ^[2]
0 0 0 RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0 0 0 THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0 0 1 IER
00
CTS
RTS
Xoff
Sleep
interrupt interrupt interrupt mode ^[3]
[3]
[3]
[3]
modem
status
interrupt
receive transmit
line status holding
interrupt register
0 1 0 FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
TX trigger DMA
trigger (LSB) ^[3] mode
(MSB) ^[3]
select ^[4]
XMIT
RCVR
FIFO reset FIFO
reset
0 1 0 ISR
01
FIFOs FIFOs INT
enabled enabled priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
0 1 1 LCR
00
divisor
latch
enable
set
break
set parity even
parity
parity
enable
stop bits
word
length
bit 1
1 0 0 MCR 00
Clock IR
Xon
select ^[3] enable ^[3] Any ^[3]
loop back OP2, INTx OP1
enable
RTS
1 0 1 LSR
60
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
1 1 0 MSR X0
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
1 1 1 SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Special Register Set ^[5]
0 0 0 DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0 0 1 DLM
XX
bit 15 bit 14 bit 13 bit 12
bit 11
bit 10
bit 9
Enhanced Register Set ^[6]
0 1 0 EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable Cont-3 Tx, Cont-2 Tx, Cont-1
IER[4:7], Rx Control Rx Control Tx, Rx
ISR[4:5],
Control
FCR[4:5],
MCR[5:7]
1 0 0 Xon-1 00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
1 0 1 Xon-2 00
bit 15 bit 14 bit 13 bit 12
bit 11
bit 10
bit 9
1 1 0 Xoff-1 00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
1 1 1 Xoff-2 00
bit 15 bit 14 bit 13 bit 12
bit 11
bit 10
bit 9
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
∆CTS
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
bit 0
bit 8
bit 0
bit 8
[1] The value shown represents the register’s initialized HEX value; X = not applicable.
[2] These registers are accessible only when LCR[7] = 0.
[3] These bits are only accessible when EFR[4] is set.
[4] This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed.
[5] The Special Register set is accessible only when LCR[7] is set to a logic 1.
[6] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
9397 750 14965
Product data sheet
Rev. 02 — 20 June 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
24 of 58