ISP1504A Datasheet, PDF(23/84 Page) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

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ISP1504A Datasheet, PDF (23/84 Pages) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

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NXP Semiconductors

ISP1504A; ISP1504C

ULPI HS USB OTG transceiver

9.3.1 Interface protection

By default, the ISP1504 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1504 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[7:0].

The interface protect feature prevents unwanted activity of the ISP1504 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1504.

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

9.3.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the

ISP1504 will assert DIR. All logic in the ISP1504 will be reset, including the analog

circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;

otherwise undeï¬ned behavior may result. When RESET_N is de-asserted (HIGH), the

DIR output will de-assert (LOW) four or ï¬ve clock cycles later. Figure 7 shows the ULPI

interface behavior when RESET_N is asserted (LOW), and when RESET_N is

subsequently de-asserted (HIGH). The behavior of Figure 7 applies only when

CHIP_SELECT_N is asserted (LOW). If RESET_N is not used, it must be tied to VCC(I/O).

CLOCK

RESET_N

DATA[7:0]

Hi-Z (input)

Hi-Z (link must drive)

Hi-Z (input)

DIR

STP

Hi-Z (input)

Hi-Z (link must drive)

Hi-Z (input)

NXT

Fig 7. Interface behavior with respect to RESET_N

004aaa720

9.3.3 Interface behavior with respect to CHIP_SELECT_N

At any time that CHIP_SELECT_N is HIGH, the ISP1504 will 3-state DATA[7:0], NXT, and

DIR, and the STP input will be ignored. The link can reuse these pins for other purposes.

When CHIP_SELECT_N is LOW, ULPI output pins operate normally. During normal

operation, the PLL is always powered, regardless of the level of CHIP_SELECT_N.

During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce

power consumption. During power-up, if CHIP_SELECT_N is LOW, the PLL is powered

and the ISP1504 operates normally.

If CHIP_SELECT_N is HIGH:

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 â 19 October 2006

23 of 84

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