PCA9506 Datasheet, PDF (21/30 Pages) NXP Semiconductors – 40-bit I2C-bus I/O port with RESET, OE, and INT

Philips Semiconductors
PCA9506
40-bit I²C-bus I/O port with RESET, OE, and INT
12. Dynamic characteristics
Table 11: Dynamic characteristics
Symbol Parameter
Conditions
f_SCL
SCL clock frequency
t_BUF
bus free time between a STOP and
START condition
t_HD;STA
hold time (repeated) START
condition
t_SU;STA
set-up time for a repeated START
condition
t_SU;STO
t_HD;DAT
t_VD;ACK
t_VD;DAT
t_SU;DAT
t_LOW
t_HIGH
t_f
set-up time for STOP condition
data hold time
data valid acknowledge time ^[2]
data valid time ^[3]
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL
signals
t_r
rise time of both SDA and SCL
signals
t_SP
pulse width of spikes that must be
suppressed by the input filter
Port timing
t_en
enable time
t_dis
disable time
t_v(Q)
data output valid time
t_su(D)
data input setup time
t_h(D)
data input hold time
Interrupt timing
t_{v(INT_N)}
t_{rst(INT_N)}
Reset
valid time on pin INT_N
reset time on pin INT_N
t_w(rst)
t_rec(rst)
t_rst
reset pulse width
reset recovery time
reset time
output
output
Standard mode
I²C-bus
Min Max
[1]
0
100
4.7
-
Fast mode I²C-bus Unit
Min
Max
0
400 kHz
1.3
- µs
4.0
-
0.6
- µs
4.7
-
0.6
- µs
4.0
0
0.1
0.1
250
4.7
4.0
[4] [5]
-
[4] [5]
-
[7]
-
-
-
3.45
3.45
-
-
-
300
0.6
0
0.1
0.1
100
1.3
0.6
20 + 0.1C_b ^[6]
- µs
- ns
0.9 µs
0.9 µs
- ns
- µs
- µs
300 ns
1000 20 + 0.1C_b ^[6] 300 ns
50
-
50 ns
-
80
-
80 ns
-
40
-
40 ns
-
250
-
250 ns
100
-
100
- ns
0.5
-
0.5
- µs
-
4
-
4 µs
-
4
-
4 µs
4
-
4
- ns
0
-
0
- ns
100
-
100
- ns
[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2] t_VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] t_VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
9397 750 14939
Product data sheet
Rev. 01 — 14 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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