PCA9506 Datasheet, PDF (1/30 Pages) NXP Semiconductors – 40-bit I2C-bus I/O port with RESET, OE, and INT

PCA9506
40-bit I²C-bus I/O port with RESET, OE, and INT
Rev. 01 — 14 February 2006
Product data sheet
1. General description
The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I²C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 800 mA to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. Output
ports are totem-pole and their logic state changes at the Acknowledge (bank change).
The device can be configured to have each input port to be masked in order to prevent it
from generating interrupts when its state changes and to have the I/O data logic state to
be inverted when read by the system master.
An open-drain interrupt (INT) output pin allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable (OE) pin 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os
as inputs. Three address select pins configure one of 8 slave addresses.
The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is specified over
the −40 °C to +85 °C industrial temperature range.
2. Features
s Standard mode (100 kHz) and Fast mode (400 kHz) compatible I²C-bus serial
interface
s 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
s 40 configurable I/O pins that default to inputs at power-up
s Outputs:
x Totem-pole (10 mA source, 25 mA sink) with controlled edge rate output structure
x Active LOW output enable (OE) input pin 3-states all outputs
x Output state change on Acknowledge
s Inputs:
x Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
x Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
x Polarity Inversion register allows inversion of the polarity of the I/O pins when read
s Active LOW reset (RESET) input pin resets device to power-up default state
s 3 programmable address pins allowing 8 devices on the same bus