TDA8043 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Satellite Demodulator and Decoder SDD

Philips Semiconductors
Satellite Demodulator and Decoder (SDD)
Product specification
TDA8043
FEATURES
• One-chip Digital Video Broadcasting (DVB) compliant
demodulator and concatenated Viterbi/Reed-Solomon
decoder with de-interleaver and de-randomizer
• 3.3 V supply voltage (up to 5 V allowed)
• Internal clock divider
• On-chip crystal oscillator
• QPSK/BPSK demodulator:
– Interpolator to handle variable symbol rates without
an external anti-aliasing filter
– On-chip Automatic Gain Control (AGC) of the analog
input I and Q baseband signals or tuner AGC control
– Two on-chip matched Analog-to-Digital Converters
(ADCs; 7 bits)
– Square-Root Raised-Cosine Nyquist filter with
programmable roll-off factor
– High maximum symbol frequency: 32 Msymbols/s
– Can be used at low channel Es/No
(Symbol energy-to-noise ratio)
– Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters
– Two carrier recovery loops enabling phase tracking of
the incoming symbols
– Different modulation schemes: Quadrature Phase
Shift Keying (QPSK) and Binary-Phase Shift Keying
(BPSK)
– Signal-to-noise ratio (S/N) estimation
– External indication of demodulator lock.
• Viterbi decoder:
– Rate ¹â„₂ convolutional code based
– Constraint length K = 7 with G₁ = 171_oct and
G₂ = 133_oct
– Supported puncturing code rates: ¹â„₂, ²â„₃, ³â„₄, ⁴⁄₅, ⁵⁄₆,
6_⁄7, 7_{⁄8 and} 8_⁄9
– 4 bits ‘soft decision’ inputs for both I and Q
– Truncation length: 144
– Automatic synchronization to correct puncturing rate
and spectral inversion
– Channel Bit Error Rate (BER) estimation from
10^−2 to 10^−8
– External indication of Viterbi synchronization lock
– Differential decoding supported.
• Reed-Solomon (RS) decoder:
– (204, 188 and T = 8) Reed Solomon code
– Automatic (I²C-bus configurable) synchronization of
bytes, transport packets and frames
– Internal convolutional de-interleaving (I = 12; using
internal memory)
– De-randomizer based on Pseudo Random Binary
Sequence (PRBS)
– External indication of RS decoder sync lock
– External indication of uncorrectable errors (transport
error indicator is set)
– Indication of the number of lost blocks
– Indication of the number of corrected blocks/bytes.
• I²C-bus interface:
– I²C-bus interface initializes and monitors the
demodulator and Forward Error Correction (FEC)
decoder with standby mode; when no I²C-bus is
used, default mode is defined
– 4-bit I/O expander for flexible access to and from the
I²C-bus
– I²C-bus configurable interrupt pin
– Standby mode for reduced power consumption.
• Package: QFP100
• Boundary scan test.
APPLICATIONS
• Demodulation and FEC for digital satellite TV.
1998 Feb 13
2