PH1955L Datasheet, PDF (2/12 Pages) NXP Semiconductors – Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.

Philips Semiconductors
PH1955L
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
PH1955L
LFPAK
plastic single-ended surface mounted package; 4 leads
4. Limiting values
Version
SOT669
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
25 °C ≤ T_j ≤ 175 °C
-
25 °C ≤ T_j ≤ 175 °C; R_GS = 20 kΩ
-
-
T_mb = 25 °C; V_GS = 5 V; see Figure 2 and 3
-
T_mb = 100 °C; V_GS = 5 V; see Figure 2
-
T_mb = 25 °C; pulsed; t_p ≤ 10 µs; see Figure 3
-
T_mb = 25 °C; see Figure 1
-
−55
−55
I_S
source current
T_mb = 25 °C
-
I_SM
peak source current
T_mb = 25 °C; pulsed; t_p ≤ 10 µs
-
Avalanche ruggedness
E_DS(AL)S non-repetitive drain-source
unclamped inductive load; I_D = 40 A;
-
avalanche energy
t_p = 0.06 ms; V_DD ≤ 55 V; R_GS = 50 Ω;
V_GS = 10 V; starting at T_j = 25 °C
E_DS(AL)R repetitive drain-source avalanche unclamped inductive load; I_D = 4 A;
[1] _-
energy
t_p = 0.06 ms; V_DD ≤ 55 V; R_GS = 50 Ω;
[2]
V_GS = 10 V
Max Unit
55
V
55
V
±15
V
40
A
28
A
160
A
75
W
+175 °C
+175 °C
40
A
160
A
80
mJ
0.8
mJ
[1] Duty cycle is limited by the maximum junction temperature.
[2] Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short
bursts, not every switching cycle.
PH1955L_1
Product data sheet
Rev. 01 — 15 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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