GTL1655DGG Datasheet, PDF (2/23 Pages) NXP Semiconductors – 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion

Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
2. Features
s Combination of D-type latches and D-type flip-flops for transceiver operation in
clocked, latched or transparent mode
s Logic level translation between LVTTL and GTL/GTL+ signals
s HIGH-drive LOW-output-impedance (100 mA/12 Ω) on Port B
s Configurable rise and fall times on Port B
s Supports live insertion (I_off, Power-up 3-state, and BIAS V_CC)
s Bus Hold on Port A inputs
s Over voltage tolerance on Port A
s Minimized switching noise through use of distributed V_CC and GND pins
s Available in TSSOP64 package
s Industrial temperature range (−40 °C to +85 °C)
s ESD protection
x HBM EIA/JESD22-A114-A exceeds 2000 V
x CDM EIA/JESD22-C101 exceeds 1000 V
s Latch-up EIA/JEDS78 exceeds 200 mA
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 2.5 ns
Symbol Parameter
Conditions
Min
Typ
Max
Unit
t_PLH
propagation delay, nAn to nBn
V_CC = 3.3 V; V_ERC = GND;
-
3.9
-
ns
V_TT = 1.5 V; V_REF = 1 V
V_CC = 3.3 V; V_ERC = GND;
-
4.4
-
ns
V_TT = 1.5 V; V_REF = 1 V
propagation delay, nBn to nAn
V_CC = 3.3 V
-
2.6
-
ns
t_PHL
propagation delay, nAn to nBn
V_CC = 3.3 V; V_ERC = GND;
-
3.1
-
ns
V_TT = 1.5 V; V_REF = 1 V
V_CC = 3.3 V; V_ERC = GND;
-
2.7
-
ns
V_TT = 1.5 V; V_REF = 1 V
propagation delay, nBn to nAn
V_CC = 3.3 V
-
4.2
-
ns
C_i
input capacitance (control pins)
V_i = V_CC or GND
-
3
-
pF
C_I/O
I/O capacitance, Port A
V_i = V_CC or GND
-
7
-
pF
I/O capacitance, Port B
V_i = V_CC or GND
-
8
-
pF
9397 750 12936
Product data
Rev. 01 — 11 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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