74HC75 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Quad bistable transparent latch

Philips Semiconductors
Quad bistable transparent latch
Product specification
74HC/HCT75
FEATURES
• Complementary Q and Q outputs
• V_CC and GND on the centre pins
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE_1-2 and LE_3-4). When LE_n-n is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE_n-n is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LE_n-n will be stored in the latches. The latched outputs
remain stable as long as the LE_n-n is LOW.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay
nD to nQ, nQ
LE_n-n to nQ, nQ
input capacitance
power dissipation capacitance per latch
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC
HCT
UNIT
11
12
ns
11
11
ns
3.5
3.5
pF
42
42
pF
December 1990
2