74HC670 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 4 x 4 register file; 3-state

Philips Semiconductors
4 x 4 register file; 3-state
Product specification
74HC/HCT670
FEATURES
• Simultaneous and independent read and write
operations
• Expandable to almost any word size and bit length
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (R_A, R_B and W_A, W_B) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D₀ to D₃). The W_A and W_B inputs determine
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q₀ to Q₃). D_n and W_n inputs are inhibited when
WE is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(R_A and R_B). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay D_n to Q_n
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o)
where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC;
for HCT the condition is V_I = GND to V_CC −1.5 V
TYPICAL
HC
23
3.5
122
HCT
23
3.5
124
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2