74HC4352 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Dual 4-channel analog multiplexer/demultiplexer with latch

Philips Semiconductors
Dual 4-channel analog
multiplexer/demultiplexer with latch
Product specification
74HC/HCT4352
FEATURES
• Wide analog input voltage range: ± 5 V.
• Low “ON” resistance:
80 Ω (typ.) at V_CC − V_EE = 4.5 V
70 Ω (typ.) at V_CC − V_EE = 6.0 V
60 Ω (typ.) at V_CC − V_EE = 9.0 V
• Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
• Typical “break before make” built in
• Address latches provided
• Output capability: non-standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4352 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4352 are dual 4-channel analog
multiplexers/demultiplexers with common select logic.
Each multiplexer has four independent inputs/outputs
(nY₀ to nY₃) and a common input/output (nZ).
The common channel select logics include two select
inputs (S₀ and S₁), an active LOW enable input (E₁), an
active HIGH enable input (E₂) and a latch enable input
(LE).
With E₁ LOW and E₂ HIGH, one of the four switches is
selected (low impedance ON-state) by S₀ and S₁. The data
at the select inputs may be latched by using the active
LOW latch enable input (LE). When LE is HIGH, the latch
is transparent. When either of the two enable inputs, E₁
(active LOW) and E₂ (active HIGH), is inactive, all analog
switches are turned off.
V_CC and GND are the supply voltage pins for the digital
control inputs (S₀, S₁, LE, E₁ and E₂). The V_CC to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY₀ to nY₃, and nZ) can swing
between V_CC as a positive limit and V_EE as a negative limit.
V_CC − V_EE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V_EE is
connected to GND (typically ground).
QUICK REFERENCE DATA
V_EE = GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PZH/ t_PZL
t_PHZ/ t_PLZ
C_I
C_PD
C_S
turn “ON” time E₁, E₂ or S_n to V_os
turn “OFF” time E₁, E₂ or S_n to V_os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
C_L = 15 pF; R_L = 1 kΩ;
V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ { (C_L + C_S ) × V_CC2 × f_o } where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ { (C_L + C_S) × V_CC2 × f_o } = sum of outputs
C_L = output load capacitance in pF
C_S = max. switch capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
December 1990
2
TYPICAL
HC
31
20
3.5
55
HCT
33
20
3.5
55
UNIT
ns
ns
pF
pF
5
5
pF
12
12
pF