74HC4051 Datasheet, PDF (2/16 Pages) NXP Semiconductors – 8-channel analog multiplexer/demultiplexer

Philips Semiconductors
8-channel analog
multiplexer/demultiplexer
Product specification
74HC/HCT4051
FEATURES
• Wide analog input voltage range: ± 5 V.
• Low “ON” resistance:
80 Ω (typ.) at V_CC − V_EE = 4.5 V
70 Ω (typ.) at V_CC − V_EE = 6.0 V
60 Ω (typ.) at V_CC − V_EE = 9.0 V
• Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
• Typical “break before make” built in
• Output capability: non-standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4051 are high-speed Si-gate CMOS
devices and are pin compatible with the “4051” of the
QUICK REFERENCE DATA
V_EE = GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PZH/ t_PZL
t_PHZ/ t_PLZ
C_I
C_PD
C_S
turn “ON” time
E to V_os
S_n to V_os
turn “OFF” time
E to V_os
S_n to V_os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4051 are 8-channel analog
multiplexers/demultiplexers with three digital select inputs
(S₀ to S₂), an active LOW enable input (E), eight
independent inputs/outputs (Y₀ to Y₇) and a common
input/output (Z).
With E LOW, one of the eight switches is selected (low
impedance ON-state) by S₀ to S₂. With E HIGH, all
switches are in the high impedance OFF-state,
independent of S₀ to S₂.
V_CC and GND are the supply voltage pins for the digital
control inputs (S₀ to S₂, and E). The V_CC to GND ranges
are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The
analog inputs/outputs (Y₀ to Y₇, and Z) can swing between
V_CC as a positive limit and V_EE as a negative limit.
V_CC − V_EE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V_EE is
connected to GND (typically ground).
CONDITIONS
C_L = 15 pF; R_L = 1 kΩ;
V_CC = 5 V
TYPICAL
HC
HCT
22
22
20
24
UNIT
ns
ns
notes 1 and 2
18
16
ns
19
20
ns
3.5
3.5
pF
25
25
pF
5
5
pF
25
25
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ { (C_L + C_S ) × V_CC2 × f_o } where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ { (C_L + C_S) × V_CC2 × f_o } = sum of outputs
C_L = output load capacitance in pF
C_S = max. switch capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
December 1990
2