74HC4017 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Johnson decade counter with 10 decoded outputs

Philips Semiconductors
Johnson decade counter with 10 decoded outputs
Product specification
74HC/HCT4017
FEATURES
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
CP₁) and an overriding asynchronous master reset input
(MR).
The counter is advanced by either a LOW-to-HIGH
transition at CP₀ while CP₁ is LOW or a HIGH-to-LOW
transition at CP₁ while CP₀ is HIGH (see also function
table).
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q₀ to Q₉),
an active LOW output from the most significant flip-flop
(Q_5-9), active HIGH and active LOW clock inputs (CP₀ and
When cascading counters, the Q_5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP₀ input of the next counter.
A HIGH on MR resets the counter to zero
(Q₀ = Q_5-9 = HIGH; Q₁ to Q₉ = LOW) independent of the
clock inputs (CP₀ and CP₁).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
t_PHL/ t_PLH
f_max
C_I
C_PD
PARAMETER
propagation delay CP₀, CP₁ to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per package
CONDITIONS
TYPICAL
HC
HCT
C_L = 15 pF; V_CC = 5 V 20
21
77
67
3.5
3.5
notes 1 and 2
35
36
UNIT
ns
MHz
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i+∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2