74HC3G06 Datasheet, PDF (2/14 Pages) NXP Semiconductors – Inverter with open-drain outputs

Philips Semiconductors
Inverter with open-drain outputs
Product specification
74HC3G06; 74HCT3G06
FEATURES
• Wide supply voltage range from 2.0 to 6.0 V
• High noise immunity
• Low power dissipation
• SOT505-2 and SOT765-1 package
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74HC3G06/74HCT3G06 is a high-speed Si-gate
CMOS device. Specified in compliance with JEDEC
standard no. 7A.
The 74HC3G06/74HCT3G06 provides three inverting
buffers.
The outputs of the 74HC3G06; 74HCT3G06 devices are
open drains and can be connected to other open-drain
outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions. For digital operation
this device must have a pull-up resistor to establish a logic
HIGH-level.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 6.0 ns.
SYMBOL
PARAMETER
CONDITIONS
t_PZL
propagation delay nA to nY
C_L = 50 pF; V_CC = 4.5 V
t_PLZ
propagation delay nA to nY
C_L = 50 pF; V_CC = 4.5 V
C_I
input capacitance
C_PD
power dissipation capacitance per buffer notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + Σ(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = total load switching outputs;
Σ(C_L × V_CC2 × f_o) = sum of the outputs.
2. For 74HC3G06 the condition is V_I = GND to V_CC.
For 74HCT3G06 the condition is V_I = GND to V_CC − 1.5 V.
TYPICAL
HC3G
9
11
1.5
4
HCT3G
9
12
1.5
4
UNIT
ns
ns
pF
pF
2003 Dec 02
2