74HC356 Datasheet, PDF (2/13 Pages) NXP Semiconductors – 8-input multiplexer/register; 3-state

Philips Semiconductors
8-input multiplexer/register; 3-state
Product specification
74HC/HCT356
FEATURES
• Non-transparent data latches
• Transparent address latch
• Easily expanding
• Complementary outputs
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT356 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT356 data selectors/multiplexers contain full
on-chip binary decoding, to select one-of-eight data
sources. The data select address is stored in transparent
latches that are enabled by a LOW on the latch enable
input LE.
Data on the 8 input lines (D₀ to D₇) is clocked into a
edge-triggered data register by a LOW-to-HIGH transition
of the clock (CP).
When the output enable input OE₁ = HIGH, OE₂ = HIGH
or OE₃ = LOW, the outputs go to the high impedance
OFF-state.
Operation of these output enable inputs does not affect the
state of the latches and register.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay
S_n, LE to Y, Y
CP to Y, Y
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
UNIT
HC HCT
24 25 ns
20 22 ns
3.5 3.5 pF
123 125 pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
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