74HC273 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Octal D-type flip-flop with reset; positive-edge trigger

Philips Semiconductors
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
74HC/HCT273
FEATURES
• Ideal buffer for MOS microprocessor or memory
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• See “377” for clock enable version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability; standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q_n) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay
CP to Q_n
MR to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
UNIT
HC HCT
15 15 ns
15 20 ns
66 36 MHz
3.5 3.5 pF
20 23 pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
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