74HC173D Datasheet, PDF (2/3 Pages) NXP Semiconductors – Quad D-type flip-flop; positive-edge trigger; 3-state

Philips Semiconductors
Quad D-type flip-flop; positive-edge trigger; 3-state
Product specification
74HC/HCT173
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I_CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
74HC
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_PHL/ t_PLH propagation delay
CP to Q_n
t_PHL
propagation delay
MR to Q_n
55 175
220
265 ns 2.0 Fig.6
20 35
44
53
4.5
16 30
37
45
6.0
44 150
190
225 ns 2.0 Fig.7
16 30
38
45
4.5
13 26
33
38
6.0
t_PZH/ t_PZL 3-state output enable time
52 150
190
225 ns 2.0 Fig.8
OE_n to Q_n
19 30
38
45
4.5
15 26
33
38
6.0
t_PHZ/ t_PLZ 3-state output disable time
52 150
190
225 ns 2.0 Fig.8
OE_n to Q_n
19 30
38
45
4.5
15 26
33
38
6.0
t_THL/ t_TLH output transition time
14 60
75
90 ns 2.0 Fig.6
5 12
15
18
4.5
4 10
13
15
6.0
t_W
clock pulse width
HIGH or LOW
80 14
16 5
14 4
100
120
20
24
17
20
ns 2.0 Fig.6
4.5
6.0
t_W
master reset pulse
width; HIGH
t_rem
removal time
MR to CP
t_su
set-up time
E_n to CP
80 14
16 5
14 4
60 −8
12 −3
10 −2
100 33
20 12
17 10
100
120
20
24
17
20
75
90
15
18
13
15
125
150
25
30
21
26
ns 2.0 Fig.7
4.5
6.0
ns 2.0 Fig.7
4.5
6.0
ns 2.0 Fig.9
4.5
6.0
t_su
set-up time
D_n to CP
60 17
75
90
12 6
15
18
10 5
13
15
ns 2.0 Fig.9
4.5
6.0
6