74HC173D Datasheet, PDF (1/3 Pages) NXP Semiconductors – Quad D-type flip-flop; positive-edge trigger; 3-state

Philips Semiconductors
Quad D-type flip-flop; positive-edge trigger; 3-state
Product specification
74HC/HCT173
FEATURES
• Gated input enable for hold (do nothing) mode
• Gated output enable control
• Edge-triggered D-type register
• Asynchronous master reset
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q₀ to Q₃)
and master reset (MR).
When the two data enable inputs (E₁ and E₂) are LOW, the
data on the D_n inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both E_n inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE₁ and OE₂) are
LOW, the data in the register is presented to the Q_n
outputs. When one or both OE_n inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OE_n transition does not affect the
clock and reset operations.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay
CP to Q_n
MR to Q_n
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC −1.5 V
TYPICAL
HC
HCT
UNIT
17
17
ns
13
17
ns
88
88
MHz
3.5
3.5
pF
20
20
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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