74F807 Datasheet, PDF (2/8 Pages) –

Philips Semiconductors FAST Products
Octal shift/count registered transceiver
with adder and parity (3–State)
Product specification
FAST 74F807
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
An, Bn
Data I/O inputs
3.5/0.166
70µA/70µA
OEA, OEB
A output enable inputs
1.0/0.033
20µA/20µA
CI/SI/CE
Carry in/serial in/clock enable input
1.0/0.033
20µA/20µA
CP
Clock input
1.0/0.033
20µA/20µA
MR
Master reset input (active low)
1.0/0.033
20µA/20µA
Sn
Select inputs
1.0/0.033
20µA/20µA
STATOUT
An, Bn
Status out output
Data I/O outputs
150/40
3mA/24mA
150/40
3mA/24mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
PIN CONFIGURATION PLCC
OEA ¹
OEB ²
A0 ³
A1 ⁴
A2 ⁵
A3 ⁶
GND ⁷
GND 8
A4 9
A5 10
A6 11
A7 12
CI/SI/CE 13
CP 14
28 MR
27 STATOUT
26 B0
25 B1
24 B2
23 B3
22 _VCC
21 _B4
20 _B5
19 _B6
18 _B7
17 _S0
16 _S1
15 _S2
STAT
A1 A0 OEB OEA MR OUT B0
4 3 2 1 28 27 26
A2 5
25 B1
A3 ⁶
24 B2
GND ⁷
23 B3
GND ⁸
A4 ⁹
PLCC
22 V_CC
21 _B4
A5 10
20 B5
A6 11
19 B6
12 13 14 15 16 17 18
A7 CI/ CP S2 S1 S0 ^B7
SI/
CE
LOGIC SYMBOL
IEC/IEEE SYMBOL
3 4 5 6 9 10 11 12
A0 A1 A2 A3 A4 A5 A6 A7
1
OEA
2
OEB
13
CI/SI/CE
28
MR
STATOUT
27
B0 B1 B2 B3 B4 B5 B6 B7
26 25 24 23 22 20 19 18
V_CC = Pin 22
GND = Pin 7, 8
13
EN3
17
0
16
M1
15
15 _STATUS
27
3
OUT
14
28
R
1
EN1
2
EN2
3
26
1
2
4
25
5
24
8
23
9
21
10
20
11
19
13
18
June 18, 1991
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