74F776 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Pi-bus transceiver

Philips Semiconductors
Pi–bus transceiver
Product specification
74F776
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with equivalent load impedances
down to 10 ohms
• High drive (100mA) open collector drivers on B port
• Reduced voltage swing (1 volt) produces less noise and reduces
power consumption
• High speed operation enhances performance of backplane buses
and facilitates incident wave switching
• Compatible with Pi–bus and IEEE 896 Futurebus standards
• Built–in precision band–gap reference provides accurate receiver
thresholds and improved noise immunity
• Controlled output ramp and multiple GND pins minimize ground
bounce
• Glitch–free power up/power down operation
• Multiple package options
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F776 is an octal bidirectional latched transceiver and is
intended to provide the electrical interface to a high performance
wired–OR bus. The B port inverting drivers are low–capacitance open
collector with controlled ramp and are designed to sink 100mA from 2
volts. The B port inverting receivers have a 100 mV threshold region
and a 4ns glitch filter.
The 74F776 B port interfaces to ’Backplane Transceiver Logic’ (BTL).
BTL features a reduced (1V to 2V) voltage swing for lower power
consumption and a series diode on the drivers to reduce capacitive
loading. Incident wave switching is employed, therefore BTL
propagation delays are short. Although the voltage swing is less for
BTL, so is its receiver threshold, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and
crosstalk, low capacitive loading, superior noise margin and low
propagation delays. This results in a high bandwidth, reliable
backplane.
The 74F776 A port has TTL 3–state drivers and TTL receivers with a
latch function. A separate high–level control voltage input (V_X) is
provided to limit the A side output level to a given voltage level (such
as 3.3V). For 5.0V systems, V_X is simply tied to V_CC.
The 74F776 has a designed feature to control the B output transitions
during power sequencing. There are two possible sequencing, They
are as follows:
1.When LE = low and OEBn = low then the B outputs are disabled until
the LE circuitry takes control. Then the B outputs will follow the A inputs,
making a maximum of one transition during power–up (or down).
2. If LE = high or OEBn = high then the B outputs will be disabled during
power–up (or down).
TYPE
74F776
TYPICAL PROPAGA-
TION DELAY
6.5ns
TYPICAL SUPPLY
CURRENT( TOTAL)
80mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C V_CC = 5V ±10%, T_amb = –40°C to +85°C
PKG DWG #
28–pin plastic DIP (600 mil)
28–pin PLCC
N74F776N
N74F776A
I74F776N
I74F776A
SOT117-2
SOT261-2
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
A0 – A7
PNP latched inputs
B0 – B7
Data inputs with threshold circuitry
OEA
A output enable input (active high)
OEB0, OEB1
B output enable inputs (active low)
LE
Latch enable input (active low)
A0 – A7
3–state outputs
B0 – B7
Open collector outputs
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
OC = Open collector.
74F (U.L.)
HIGH/LOW
3.5/0.117
5.0/0.167
1.0/0.033
1.0/0.033
1.0/0.033
150/40
OC/166.7
LOAD VALUE
HIGH/LOW
70µA/70µA
100µA/100µA
20µA/20µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
December 19, 1990
2
853 1121 01321