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74F676 Datasheet, PDF (2/10 Pages) NXP Semiconductors – 16-bit serial/parallel-in, serial-out shift register 3-State
Philips Semiconductors
16-bit serial/parallel-in, serial-out shift register (3-State)
Product specification
74F676
FEATURES
• 16-bit parallel-to-serial conversion
• 16-bit serial-in, serial-out
• Chip select control
• Power supply current 48mA typical
• Shift frequency 110MHz tyical
• Available in 300mil-wide 24-pin Slim DIP package
DESCRIPTION
The 74F676 contains 16 flip-flops with provision for synchronous
parallel or serial entry and serial output. When the mode (M) input is
High, information present on the parallel data (D0–D15) inputs is
entered on the falling edge of the clock pulse (CP) input signal.
When M is Low, data is shifted out of the most significant bit position
while information present on the serial (SI) input shifts into the least
significant bit position. A High signal on the chip select (CS) input
prevents both parallel and serial operations.
The 16 bit shift register operates in one of three modes, as indicated
in the shift register Function Table.
Hold: A High signal on the Chip Select (CS) input prevents clocking
and data is stored in the 16 registers.
Serial load: Data present on the SI pin shifts into the register on the
falling edge of CP. Data enters the Q0 position and shifts toward
Q15 on successive clocks finally appearing on the SO pin.
Parallel load: Data present on D0–D15 is entered into the register
on the falling edge of CP. The SO output represents the Q15 register
output.
To prevent false clocking, CP must be Low during a Low-to-High
transition of CS.
PIN CONFIGURATION
CS 1
CP 2
NC 3
SI 4
M5
SO 6
D0 7
D1 8
D2 9
D3 10
D4 11
GND 12
24 VCC
23 D15
22 D14
21 D13
20 D12
19 D11
18 D10
17 D9
16 D8
15 D7
14 D6
13 D5
SF01209
TYPE
74F676
TYPICAL fMAX
110MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
48mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
24-Pin Plastic Slim
DIP (300mil)
N74F676N
SOT222-1
24-Pin Plastic SOL
N74F676D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
D0–D15
Parallel data inputs
1.0/1.0
SI
Serial data input
1.0/1.0
CS
Chip Select input (active Low)
1.0/1.0
CP
Clock Pulse input (active falling edge)
1.0/1.0
M
Mode select input
1.0/1.0
SO
Serial data output
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1mA/20mA
1990 Apr 18
2
853–0284 99394