74F646 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Octal transceiver/register, non-inverting 3-State

Philips Semiconductors
Transceivers/registers
Product specification
74F646/A/74F648/A
FEATURES
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70µA in high
and low states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• Controlled ramp outputs for 74F646A/74F648A
• 3-state outputs
• 300 mil wide 24-pin slim dip package
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE is active low. In the
isolation mode (OE = high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
74F646/74F648
74F646A/74F648A
ORDERING INFORMATION
DESCRIPTION
24–pin plastic slim DIP
(300mil)
24–pin plastic SOL
TYPICAL f_max
115MHz
185MHz
TYPICAL SUPPLY CURRENT ( TOTAL)
140mA
105mA
ORDER CODE
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F646N, N74F646AN, N74F648N, N74F648AN
N74F646D, N74F646AD, N74F648D, N74F648AD
PKG DWG #
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
A0 – A7, B0 – B7
A and B inputs
3.5/0.116
CPAB
A–to–B clock input
1.0/0.033
CPBA
B–to–A clock input
1.0/0.033
SAB
A–to–B select input
1.0/0.033
SBA
B–to–A select input
1.0/0.033
DIR
Data flow directional control enable input
1.0/0.033
OE
Output enable input
1.0/0.033
A0 – A7, B0 – B7
A, B outputs for N74F646A/N74F648A
750/80
A0 – A7, B0 – B7
A, B outputs for N74F646/N74F648
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
750/106.7
LOAD VALUE HIGH/
LOW
70µA/70µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
15mA/48mA
15mA/64mA
1990 Sep 25
2
853-1124 00515