74F620 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Octal bus transceiver, inverting 3tate

Philips Semiconductors
Transceivers
Product specification
74F620/74F623
74F620 Octal Bus Transceiver, Inverting (3-State)
74F623 Octal Bus Transceiver, Non-Inverting (3-State)
FEATURES
• High-impedance NPN base inputs for reduced loading
(70µA in High and Low states)
• Ideal for applications which require high output drive and minimal
bus loading
• Octal bidirectional bus interface
• 3-State buffer outputs sink 64mA and source 15mA
• 74F620, inverting
• 74F623, non-inverting
DESCRIPTION
The 74F620 is an octal transceiver featuring inverting 3-State
bus-compatible outputs in both send and receive directions. The
outputs are capable of sinking 64mA and sourcing up to 15mA,
providing very good capacitive drive characteristics. The 74F623 is
a non-inverting version of the 74F620.
These octal bus transceivers are designed for asynchronous
two-way communication between data buses. The control function
implementation allows for maximum flexibility in timing.
These devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic levels at the
Enable inputs (OEBA and OEAB). The Enable inputs can be used to
disable the device so that the buses are effectively isolated.
The dual-enable configuration gives the 74F620 and 74F623 the
capability to store data by the simultaneous enabling of OEBA and
OEAB. Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are enabled and all
other data sources to the two sets of the bus lines are at high
impedance, both sets of bus lines (16 in all) will remain in their last
states.
TYPE
74F620
74F623
TYPICAL
PROPAGATION
DELAY
3.5ns
4.5ns
TYPICAL SUPPLY CURRENT
(TOTAL)
80mA
105mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
20-pin plastic DIP N74F620N, N74623N
20-pin plastic SOL N74F620D, N74623D
PKG DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
A0 - A7, B0 - B7
Data inputs
OEBA, OEAB
Output Enable inputs
A0 - A7
Data outputs
B0 - B7
Data outputs
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F(U.L.)
HIGH/LOW
3.5/1.16
1.0/0.033
150/40
750/106.7
LOAD VALUE
HIGH/LOW
70µA/70µA
20µA/20µA
3mA/24mA
15mA/64mA
PIN CONFIGURATION – 74F620
OEAB 1
A0 ²
A1 ³
A2 4
A3 ⁵
A4 6
A5 ⁷
A6 8
A7 ⁹
GND 10
20 V_CC
19 OEBA
18 B0
17 B1
16 B2
15 ^B3
14 B4
13 B5
12 B6
11 B7
SF01124
PIN CONFIGURATION – 74F623
OEAB 1
A0 ²
A1 ³
A2 4
A3 ⁵
A4 6
A5 ⁷
A6 8
A7 ⁹
GND 10
20 V_CC
19 OEBA
18 B0
17 B1
16 B2
15 ^B3
14 B4
13 B5
12 B6
11 B7
SF01124
1990 Apr 6
2
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