74F579 Datasheet, PDF (2/14 Pages) NXP Semiconductors – 8-bit bidirectional binary counter 3-State

Philips Semiconductors
8-bit bidirectional binary counter (3-State)
Product specification
74F579
FEATURES
• Fully synchronous operation
• Multiplexed 3-State I/O ports for bus oriented applications
• Built in cascading carry capability
• U/D pin to control direction of counting
• Separate pins for Master reset and Synchronous operation
• Center power pins to reduce effects of package inductance
• Count frequency 115MHz Typ
• Supply current 100mA Typ
• See 74F269 for 24-pin separate I/O port version
• See 74F779 for 16-pin version
DESCRIPTION
The 74F579 is a fully synchronous 8-stage Up/Down Counter with
multiplexed 3-State I/O ports for bus-oriented applications. It
features a preset capability for programmable operation, carry
look-ahead for easy cascading and a U/D input to control the
direction of counting. All state changes, except for the case of
asynchronous reset, are initiated by the rising edge of the clock.
TC output is not recommended for use as a clock or asynchronous
reset due to the possibility of decoding spikes.
PIN CONFIGURATION
CP
I/O0 1
I/O1 2
I/O2 3
I/O3 4
GND ⁵
I/O4 6
I/O5 7
I/O6 8
I/O7 9
10
MR
20 _SR
19 _CEP
18 _CET
17 VCC
16 _TC
15 _U/D
14 _PE
13 _CS
12 _OE
11
SF01085
ORDERING INFORMATION
TYPE
74F579
TYPICAL f_MAX
115MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
100mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
PKG DWG #
20-Pin Plastic DIP
N74F579N
SOT146-1
20-Pin Plastic SOL
N74F579D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
Data Inputs
I/O_n
Data Outputs
3.5/1.0
150/40
PE
Parallel Enable input (active Low)
1.0/1.0
U/D
Up/Down count control input
1.0/1.0
MR
Master Reset input (active Low)
1.0/1.0
SR
Synchronous Reset input (active Low)
1.0/1.0
CEP
Count Enable Parallel input (active Low)
1.0/1.0
CET
Count Enable Trickle input (active Low)
1.0/1.0
CS
Chip Select input (active Low)
1.0/1.0
OE
Output Enable input (active Low)
1.0/1.0
CP
Clock input (active Rising Edge)
1.0/1.0
TC
Terminal Count Output (active Low)
50/33
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
70µA/0.6mA
3.0mA/24mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1992 May 04
2
853-0377 06639