SAA5244A Datasheet, PDF (19/32 Pages) NXP Semiconductors – Integrated VIP and teletext decoder IVT1.1

Philips Semiconductors
Integrated VIP and teletext decoder
(IVT1.1)
Product specification
SAA5244A
Register maps
SAA5244A mode registers R0 to R11 are shown in Table 2. R0 to R10 are WRITE only; R11 is READ/WRITE.
Register map (R3), for page requests, is shown in detail in Table 3.
Table 2 Register map
REGISTER
Adv.
0
control
Mode
1
Page
2
request
address
Page
3
request
data
Display
5
control
(normal)
Display
6
control
(newsflash
/subtitle)
Display
7
mode
Cursor
9
row
Cursor
10
column
Cursor
11
data
Device
11B
status
D7
X24
POS
VCS TO
SCS
−
D6
D5
FREE
RUN PLL
−
AUTO
ODD/
EVEN
ACQ
ON/OFF
−
−
D4
D3
DISABLE −
HDR
ROLL
−
DEW/
FULL
FIELD
−
TB
−
−
−
PRD4
PRD3
D2
D1
DISABLE −
ODD/
EVEN
TCS
T1
ON
D0
R11/R11B
SELECT
T0
START START START
COLUMN COLUMN COLUMN
SC2
SC1
SC0
PRD2
PRD1
PRD0
−
BKGND
OUT
−
BKGND
IN
−
COR
OUT
BKGND BKGND COR
OUT
IN
OUT
−
COR
IN
COR
IN
−
TEXT
OUT
TEXT
OUT
−
TEXT
IN
TEXT
IN
−
PON
OUT
PON
OUT
−
PON
IN
PON
IN
STATUS
TOP
−
SUPPL.
BLAST
SUPPL.
ROW 24
−
CURSOR REVEAL
ON
ON
−
−
CLEAR A0
MEM.
SUPPL. C5
ROW 0
D6
D5
BOTTOM
HALF
−
R4
DOUBLE
HEIGHT
−
R3
BOX
24
−
R2
C4
C3
C2
D4
D3
D2
BOX
1-23
−
R1
C1
D1
BOX
0
−
R0
C0
D0
625/525
SYNC
ROM
VER R4
ROM
VER R3
ROM
VER R2
ROM
VER R1
ROM
VER R0
TEXT
VCS
SIGNAL SIGNAL
QUALITY QUALITY
Notes to Table 2
1. ‘− ‘ indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 to D1 of registers R1, R5 and R6
which are set to logic 1.
3. All memory is cleared to ‘space’ (00100000) on power-up, except row 0 column 7 chapter 0, which is ‘alpha’ white
(00000111) as the acquisition circuit is enabled but the page is on hold.
4. TB must be set to logic 0 for normal operation.
5. The I²C slave address is 0010001
March 1992
19