SAA7706H Datasheet, PDF (18/52 Pages) NXP Semiconductors – Car radio Digital Signal Processor (DSP)

Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Product specification
SAA7706H
8.4 Signal path from FM_MPX input to IAC and
stereo decoder
The FM_MPX signal is after selection available at one of
three ADCs (ADC1, 2 and 3). The multiplex FM signal is
converted to the digital domain in ADC1, 2 and 3 through
a bitstream ADC. Improved performance for FM stereo
can be achieved by means of adapting the noise shaper
curve of the ADC to a higher bandwidth.
The first decimation takes place in two down-sample
filters. These decimation filters are switched by means of
the I²C-bus bit wide_narrow in the wide or narrow band
position. In the event of FM reception it must be in the
narrow position.
After selection of one of the ADCs, the FM_MPX path it is
followed by the IAC and the FM stereo decoder. One of the
two MPX filter outputs contains the multiplex signal with a
frequency range of 0 to 60 kHz. The overall low-pass
frequency response of the decimation filters is shown in
Fig.10.
0
handbook,_αfull pagewidth
(dB)
− 20
MGT466
− 40
− 60
− 80
−100
−120
−140
0
100
200
300
400
500
f (kHz)
Fig.10 Overall frequency response of ADC1, ADC2 and decimation filters.
2001 Mar 05
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