SAA7706H Datasheet, PDF (17/52 Pages) NXP Semiconductors – Car radio Digital Signal Processor (DSP)

Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Product specification
SAA7706H
8.3 Signal path for level information
For FM weak signal processing, for AM and FM purposes
(absolute level and multipath) a level input is implemented
(pin LEVEL). In the event of radio reception the clocking of
the filters and the level-ADC is based on a 38 kHz
sampling frequency. A DC input signal is converted by a
bitstream sigma-delta ADC followed by a decimation filter.
The input signal has to be obtained from a radio part. The
tuner must deliver the level information of either AM or FM
to pin LEVEL.
The input signal for level must be in the range 0 to 3.3 V
(V_VDACP − V_VDACN). The 9-bit level-ADC converts this
input voltage in steps with a resolution better than at least
14 mV over the 3.3 V range.
The tolerance on the gain is less than 2%. The MSB is
always logic 0 to represent a positive level. Input level
span can be increased by an external resistor tap. The
high input impedance of the level-ADC makes this
possible.
The decimation filter reduces in the event of an 38 kHz
based clocking regime the bandwidth of the incoming
signal to a frequency range of 0 to 29 kHz with a resulting
f_s = 76 kHz. The response curve is given in Fig.9.
The level information is sub-sampled by the DSP1 to
obtain a field strength and a multipath indication. These
values are stored in the coefficient or data RAM. Via the
I²C-bus they can be read and used in other microcontroller
programs.
10
handbook, full pagewidth
α
(dB)
0
MGT465
− 10
− 20
− 30
− 40
− 50
− 60
0
10
20
30
40
50
60
70
80
f (kHz)
Fig.9 Frequency response level-ADC and decimal filter.
2001 Mar 05
17