P89LPC932A1 Datasheet, PDF (17/64 Pages) NXP Semiconductors – 8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM

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Table 4: Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. _MSB
LSB
Reset value
Hex Binary
TISE2
CCU interrupt status encode DEH
-
-
-
-
-
ENCINT. ENCINT. ENCINT. 00
xxxx x000
register
2
1
0
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TL2
CCU timer low
CCH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00
0000 0000
TOR2H CCU reload register high
CFH
00
0000 0000
TOR2L CCU reload register low
CEH
00
0000 0000
TPCR2H Prescaler control register
CBH
-
-
-
-
-
-
TPCR2H. TPCR2H. 00
xxxx xx00
high
1
0
TPCR2L Prescaler control register low CAH TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. 00
7
6
5
4
3
2
1
0
0000 0000
TRIM
Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[5] [4]
WDCON Watchdog control register
A7H PRE2 PRE1 PRE0
-
-
WDRUN WDTOF WDCLK
[6] [4]
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1 Watchdog feed 1
C2H
WFEED2 Watchdog feed 2
C3H
[1] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2] All ports are in input only (high-impedance) state after power-up.
[3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.
[4] The only reset source that affects these SFRs is power-on reset.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.