SAA7282 Datasheet, PDF (16/25 Pages) NXP Semiconductors – Terrestrial Digital Sound Decoder TDSD2

Philips Semiconductors
Terrestrial Digital Sound Decoder (TDSD2)
Product specification
SAA7282
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Digital filter specification
f_s
PR
SBA
output sample frequency
pass band ripple
stop band attenuation
−
at 0 Hz to 15 kHz
−
at f ≥17 kHz
30
128
−
kHz
−
±0.01
dB
−
−
dB
Digital de-emphasis
DEV
deviation from ideal
−
ANALOG SECTION (measured at V_DD = 5 V and T_amb = 25 °C)
−
±0.09
dB
Reference voltage buffer
VRC output
V_rc
voltage reference at VRC
see Fig.10
0.45V_DDAR 0.5V_DDAR 0.55V_DDAR V
DACs
V_REF input
V_ref
reference input voltage
−
0.5V_DD −
V
Switching operational amplifiers
C_L
output load capacitance
R_L
output load resistance
Z_O
output impedance
−
−
300
pF
3
−
−
kΩ
−
150
−
Ω
G
output gain
−0.35
0
+0.35
dB
PSRR
power supply rejection ratio
−
40
−
dB
External inputs selected (FML, FMR, EXTL, EXTR)
V_ain
input voltage level (RMS value)
S/N
signal-to-noise ratio (relative to FM or EXT
1 V RMS, unity gain)
−
−
1.1
V
90
100
−
dB
THD
total harmonic distortion (unity FM or EXT
gain, O/P = 1 V RMS)
−
−90
−70
dB
CHM
channel matching
FM or EXT, 1 kHz
−
0
0.5
dB
NICAM inputs selected (INTL, INTR)
V_ain
THD+N
input voltage level (RMS value) at 0 dB; V_REF = 2.5 V 0.9
total harmonic distortion plus NICAM 728; notes 2 −
noise
and 3
1.0
1.1
V
−80
−75
dB
CHM
channel matching
0 dB, 1 kHz
−
0
0.5
dB
DIGS
digital silence level
MUTE on
−
−80
−
dB
Timing (all timing values refer to V_IH and V_IL levels)
DATA with respect to PCLK (see Fig.7)
t_SU;DAT
t_HD;DAT
data set-up time
data hold time
100
−
−
ns
250
−
−
ns
July 1993
16