SAA7282 Datasheet, PDF (10/25 Pages) NXP Semiconductors – Terrestrial Digital Sound Decoder TDSD2

Philips Semiconductors
Terrestrial Digital Sound Decoder (TDSD2)
Product specification
SAA7282
CFC
Signals a change of configuration at the 16-frame
boundary. It is cleared to logic 1 by the I²C-bus reading the
status register.
E7 to E0
This is an error count byte which counts the number of
error flags in a 128 ms period. The register is updated
every 128 ms.
AD10 to AD0
These are the additional data bits from the transmission
and are updated every 1 ms.This provides a data capacity
of 11 kbit/s.
SAD
SAD is the 'status additional data' bit. This is set to logic 1
when new bits AD10 to AD0 are latched into the I²C-bus
registers. It is automatically reset to logic 0 when
AD_BYTE_1 is read by the bus master.
OVW
OVW is the overwrite indicator for the additional data.
This bit is set when the transmission overwrites additional
data bits which have not been read by the bus master.
This bit is automatically reset to logic 0 when AD_BYTE_1
is read by the bus master.
CI1 to CI2
These represent the CI bits which are extracted by a
majority logic process from the parity checks of the last ten
samples in a frame (samples 55 to 64). CI1 will be
conveyed by the parity grouping of samples 55 to 59 and
CI2 will be conducted by the parity grouping of samples 60
to 64. Both parity groups will be even for UK transmissions
such that CI2 = logic 0 and CI1 = logic 0. The
transmissions of countries following the specification
issued by the EBU (Document SPB424; “Digital sound
transmissions in terrestrial television”) will allow odd or
even parity groups, thus providing an additional 2 kbit/s
data capacity.
Table 6 Indicator bits functional truth table.
TRANSMISSION
C1
C2
Stereo
0
0
M1 + M2
0
1
M1 + data
1
0
Transparent data
1
1
Any currently undefined combination of C1, C2, C3
Decoder unsynchronized (OS = logic 0)
C3
S/M
D/S
VDSP
OS
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
note 1 note 1
0
0
Note
1. Holds last value before synchronization loss or stereo (S/M = logic 1; D/S = logic 0) if synchronization not achieved
since power-on reset.
July 1993
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