80C31 Datasheet, PDF (16/30 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = 5V ±10%, V_SS = 0V^{1, 2, 3}
24MHz CLOCK
VARIABLE CLOCK⁴
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
MIN MAX UNIT
1/t_CLCL
1
Oscillator frequency
3.5
Speed versions : P (24MHz)
3.5
24
: Y (33MHz)
33
MHz
3.5
33
t_LHLL
1
t_AVLL
1
t_LLAX
1
t_LLIV
1
t_LLPL
1
t_PLPH
1
t_PLIV
1
t_PXIX
1
t_PXIZ
1
t_AVIV
1
t_PLAZ
1
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
43
2t_CLCL–40
21
ns
17
t_CLCL–25
5
ns
17
t_CLCL–25
ns
102
4t_CLCL–65
55
ns
17
t_CLCL–25
5
ns
80
3t_CLCL–45
45
ns
65
3t_CLCL–60
30
ns
0
0
0
ns
17
t_CLCL–25
5
ns
128
5t_CLCL–80
70
ns
10
10
10
ns
t_RLRH
2, 3
t_WLWH
2, 3
t_RLDV
2, 3
t_RHDX
2, 3
t_RHDZ
2, 3
t_LLDV
2, 3
t_AVDV
2, 3
t_LLWL
2, 3
t_AVWL
2, 3
t_QVWX
2, 3
t_WHQX
2, 3
t_QVWH
3
t_RLAZ
2, 3
t_WHLH
2, 3
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
150
6t_CLCL–100
82
ns
150
6t_CLCL–100
82
ns
118
5t_CLCL–90
60
ns
0
0
0
ns
55
2t_CLCL–28
32
ns
183
8t_CLCL–150
90
ns
210
9t_CLCL–165
105 ns
75
175 3t_CLCL–50 3t_CLCL+50
40
140
ns
92
4t_CLCL–75
45
ns
12
t_CLCL–30
0
ns
17
t_CLCL–25
5
ns
162
7t_CLCL–130
80
ns
0
0
0
ns
17
67
t_CLCL–25
t_CLCL+25
5
55
ns
t_CHCX
5
t_CLCX
5
t_CLCH
5
t_CHCL
5
Shift Register
High time
Low time
Rise time
Fall time
17
17
t_CLCL–t_CLCX
ns
17
17
t_CLCL–t_CHCX
ns
5
5
ns
5
5
ns
t_XLXL
4
Serial port clock cycle time
505
12t_CLCL
360
ns
t_QVXH
4
Output data setup to clock rising edge 283
10t_CLCL–133
167
ns
t_XHQX
4
Output data hold after clock rising edge 3
2t_CLCL–80
ns
t_XHDX
4
Input data hold after clock rising edge
0
0
0
ns
t_XHDV
4
Clock rising edge to input data valid
283
10t_CLCL–133
167 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 15.
1996 Aug 16
16