80C31 Datasheet, PDF (15/30 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = 5V ±10%, V_SS = 0V^{1, 2, 3}
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
UNIT
1/t_CLCL
1
Oscillator frequency
Speed versions : C, G
3.5
16
MHz
t_LHLL
1
t_AVLL
1
t_LLAX
1
t_LLIV
1
t_LLPL
1
t_PLPH
1
t_PLIV
1
t_PXIX
1
t_PXIZ
1
t_AVIV
1
t_PLAZ
1
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in⁴
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in⁴
PSEN low to address float
85
2t_CLCL–40
ns
22
t_CLCL–40
ns
32
t_CLCL–30
ns
150
4t_CLCL–100
ns
32
t_CLCL–30
ns
142
3t_CLCL–45
ns
82
3t_CLCL–105
ns
0
0
ns
37
t_CLCL–25
ns
207
5t_CLCL–105
ns
10
10
ns
t_RLRH
2, 3
t_WLWH
2, 3
t_RLDV
2, 3
t_RHDX
2, 3
t_RHDZ
2, 3
t_LLDV
2, 3
t_AVDV
2, 3
t_LLWL
2, 3
t_AVWL
2, 3
t_QVWX
2, 3
t_WHQX
2, 3
t_QVWH
3
t_RLAZ
2, 3
t_WHLH
2, 3
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
275
6t_CLCL–100
ns
275
6t_CLCL–100
ns
147
5t_CLCL–165
ns
0
0
ns
65
2t_CLCL–60
ns
350
8t_CLCL–150
ns
397
9t_CLCL–165
ns
137 239
3t_CLCL–50
3t_CLCL+50
ns
122
4t_CLCL–130
ns
13
t_CLCL–50
ns
13
t_CLCL–50
ns
287
7t_CLCL–150
ns
0
0
ns
23
103
t_CLCL–40
t_CLCL+40
ns
t_CHCX
5
t_CLCX
5
t_CLCH
5
t_CHCL
5
Shift Register
High time
Low time
Rise time
Fall time
20
20
t_CLCL–t_CLCX
ns
20
20
t_CLCL–t_CHCX
ns
20
20
ns
20
20
ns
t_XLXL
4
Serial port clock cycle time
750
12t_CLCL
ns
t_QVXH
4
Output data setup to clock rising edge
492
10t_CLCL–133
ns
t_XHQX
4
Output data hold after clock rising edge
8
2t_CLCL–117
ns
t_XHDX
4
Input data hold after clock rising edge
0
0
ns
t_XHDV
4
Clock rising edge to input data valid
492
10t_CLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interfacing.
1996 Aug 16
15