SA56004X Datasheet, PDF (15/23 Pages) NXP Semiconductors – 1 Degrees Celcious accurate, SMBus-compatible, 8-pin, remote/local digital temperature sensor with over temperature alarms

Philips Semiconductors
±1 °C accurate, SMBus-compatible, 8-pin, remote/local
digital temperature sensor with over temperature alarms
Product data sheet
SA56004X
Event E: Master should correct the conditions that caused the
ALERT output to be triggered. For instance, the fan is started,
setpoint levels are adjusted.
Event F: Master resets the ALERT mask bit 7 in the Configuration
register.
ALERT output in SMBus alert mode
When several slave devices share a common interrupt line, an
SMBus alert line is implemented. The SA56004X is designed to
accommodate the Alert interrupt detection capability of the SMBus
2.0 Alert Response Address (ARA) protocol, defined in SMBus
specification 2.0. This procedure is designed to assist the master in
resolving which slave device generated the interrupt and in servicing
the interrupt while minimizing the time to restore the system to its
proper operation. Basically, the SMBus provides Alert response
interrupt pointers in order to identify slave devices which have
caused the Alert interrupt. When the ARA command is received by
all devices on the SMBus, the devices pulling the SMBus alert line
LOW send their device addresses to the master; await an
acknowledgement and then release the alert line. This requirement
to disengage the SMBus alert line prevents locking up the alert line.
The SA56004X complies with this ARA disengagement protocol by
setting the ALERT mask bit 7 in the Configuration register at address
09h after successfully sending out its address in response to an
ARA command and releasing the ALERT output. Once the mask bit
is activated, the ALERT output will be disabled until enabled by
software. In order to enable the ALERT the master must read the
Status register, at address 02h, during the interrupt service routine
and then reset the ALERT mask bit 7 in the Configuration register to
‘0’ at the end of the interrupt service routine (See Figure 14).
In order for the SA56004X to respond to the ARA command, the bit
D0 in the ALERT mode register must be set LOW.
ALERT mask bit 7 and the ALERT mode bit D0 are both LOW for
the POR default.
Remote Temp
High Limit
Remote
Diode Temp
SA56004–X
ALERT pin
Status Register
Bit 4(RHIGH)
A
B
C
D
SL02057
Figure 14. ALERT pin in SMBus Alert mode
The following events summarize the ALERT output interrupt
operation in the SMBus alert mode:
Event A: Master senses the ALERT line being LOW.
Event A to B: Master sends a read command using the common
7-bit Alert Response Address (ARA) of 0001 100.
Event A to B: Alerting device(s) return ACK signal and their
addresses using the I²C Arbitration (the device with the lowest
address value sends its address first. The master can repeat the
alert reading process and work up through all the interrupts).
Event B: Upon the successful completion of returning address, the
SA56004X resets its ALERT output (to OFF) and sets the Alert
Mask bit 7 in its configuration register.
Event C: Master should read the device status register to identify
and correct the conditions that caused the Alert interruption. The
status register is reset.
Event D: Master resets the Alert Mask bit 7 in the configuration
register to enable the device Alert output interruption.
Note: The bit assignment of the returned data from the ARA
reading is listed in Table 14. If none of the device on the bus is
alerted then the returned data from ARA reading will be FFh
(1111 1111).
Table 14. ALERT response bit assignment
Alert
response
bit
7 (MSB)
6
5
4
3
2
1
0
Device
address
bit
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
1
Function
Address bit 6 (MSB) of alerted device
Address bit 5 of alerted device
Address bit 4 of alerted device
Address bit 3 of alerted device
Address bit 2 of alerted device
Address bit 1 of alerted device
Address bit 0 of alerted device
Always ‘1’
2004 Oct 06
15